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Ready to fetch Nicholas Lucindo's technical experience.
Fetching Who I Am
My Background
Born and raised in Florida, my childhood mostly comprised of wrangling alligators. As I grew older, I came to realize that my passion was not in gator-wrangling, but in problem solving. I'm curious, creative, and extroverted, leading me to engineering.
While every engineer needs a strong technical foundation, I believe I stand out through my love for collaboration, genuine curiosity, and immense passion.
One minute, it's 10:00pm. The next, it's 1:00am and I'm 30 minutes into a YouTube video about minor synthesis-based timing optimizations.
Open Project Space Cohort Graduation, May 2025
Astera Labs Design & Verification Interns, July 2026
Naval Nuclear Labs Internship, Summer 2025
IEEE Rising Stars Conference, January 2026
Pitching My Startup: Quantum Day, September 2025
Astera Labs Hackathon, Summer 2026
My Education
Master of Science in Electrical and Computer Engineering
University of Florida
January 2027 - December 2027Continued exploration of computer architecture, low-level systems, and advanced verification methodologies.
Bachelor of Science in Computer Engineering
University of Florida
August 2023 - December 2026Deep focus on RTL design, computer architecture, and embedded systems. Coursework in VHDL, SystemVerilog, FPGA architecture, and verification methodologies.
Associates of Arts
St. Petersburg College
August 2021 - May 2023General coursework at the college level, preparing me for my undergraduate engineering degree.
Decoding My Experience
Internships and Research
Astera Labs
Design Verification Intern, Summer 2026
Upcoming: May 2026 - August 2026Skills: SystemVerilog, UVM, Coverage Testing
- Building a configurable UVM environment that conditionally assembles the entire testbench (drivers, stimulus, VIPs, subscribers, scoreboard) to match each generated DUT configuration, eliminating per-config hand-wiring
- Establishing fully automated regression infrastructure to independently verify a reusable internal IP library never previously tested standalone, running the regressions continuously to catch IP-level bugs before full-chip integration
Florida Institute of National Security (FINS)
Undergraduate Research Assistant
January 2025 - February 2026Skills: RTL Design, High Performance Computing, Reverse Engineering
- Conducted faculty-advised research in hardware specification reverse engineering by leveraging open-source LLMs
- Tested accuracy of LLM’s HDL code generation and compiled training data for reverse engineering model
UF ECE Research Department
Undergraduate Research Assistant
January 2025 - PresentSkills: Formal Verification, C++, Z3, Disassembly, Ghidra
- Developing formal analysis tool to lift binaries to SMT (Z3) constraints for ISA-level semantic equivalence checking
- Translating P-Code IR (Ghidra/pypcode) into SMT-LIB2 representations for automated reasoning across ISAs
Naval Nuclear Laboratory
FPGA Engineering Intern, Summer 2025
May 2025 - July 2025Skills: IP Integration, Networking, Test Automation, FPGAs, Vivado
- Developed new FPGA communication strategy to improve shipboard data transmission speeds by over 100%
- Ran end-to-end tests across interconnected boards to validate custom protocol in a realistic hardware environment
- Outlined a proof-of-concept through SystemVerilog simulations, pitched to company leadership to garner support
Projects and Businesses
ZeroSlack
Solo-Developed ZeroSlack: Leetcode for SystemVerilog Problems
December 2025Skills: Testbench Design, SystemVerilog, Verilator, Full-Stack Web Dev
Link: https://zeroslack.dev
- Built ZeroSlack: Full-stack SystemVerilog learning platform with real-time HDL compilation, Verilator integration, and Docker-isolated code execution
- Deployed production system: Railway backend with containerized simulation pipeline, Cloudflare Pages frontend, MongoDB user tracking, and Google OAuth
Roleo
Founded Accelerator-Backed Startup
December 2025Skills: Testbench Design, SystemVerilog, Verilator, Full-Stack Web Dev
Link: https://roleo.org
- Founded and engineered Roleo, a two-sided hiring platform connecting universities with adjunct faculty to streamline academic hiring
- Translated real hiring pain points into core product workflows, iterating from initial architecture to a validated MVP
Executing: Working With Me
Senior Product Scientist, Ocean Optics
"At less than 10 weeks into the project he has arguably moved beyond where the prior team had gone over the course of a year... he offers a valuable combination of sober discernment, mature professionalism, focused and fast outputs, and the ability to balance new-and-old tools for the job at hand."
- Derek Guenther
Senior Advisor Engineer, Naval Nuclear Laboratory
"Nicholas quickly grasped the assignment’s objectives and learned the FPGA development tools and programming languages required for the project. Once proficient, Nicholas created a simulation of an experimental FPGA-based algorithm in the SystemVerilog language. Nicholas invested extra effort to ensure that the simulation was configurable and scalable, and in the process, enabled testing of the algorithm at a larger scale than was previously possible. Nicholas also developed a working demonstration of the algorithm on Xilinx evaluation boards."
- [Anonymized for Security, Contact Me for Details]
Software Engineering Manager, Naval Nuclear Laboratory
"Nick has demonstrated superior communication skills, communicating effectively with his mentors, managers, and other interns and co-ops to progress the project... Nick also demonstrated flexibility and resourcefulness working around limitations with available computers that could operate on a development computer network with limited availability."
- [Anonymized for Security, Contact Me for Details]
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